Error 12007 top level design entity test is undefined năm 2024

Error [176603]: Cannot place node CLK_125M_SEC at IOPAD_X119_Y43_N0 because it cannot drive the node HDP:U1|CLK_RESET_GEN:clk_rst|CLK125M_SEL:U3|CLK125 M_SEL_altclkctrl_lef:CLK125M_SEL_altclkctrl_lef_co mponent|sd2 placed at CLKSEL_G0

Error [176603]: Cannot place node CLK_125M at IOPAD_X0_Y52_N0 because it cannot drive the node HDP:U1|CLK_RESET_GEN:clk_rst|CLK125M_SEL:U3|CLK125 M_SEL_altclkctrl_lef:CLK125M_SEL_altclkctrl_lef_co mponent|sd2 placed at CLKSEL_G4

After getting the error message, I tried also to use a constant value for the SELECT ['0'], but I received again the same error.

My questions are: - In general: Is it possible to drive these two input clock pins through a CLKCTRL block? - Do I have anything wrong in the ALTCLKCTRL block MegaWizard configuration? - Do I I have something wrong in the way I use the ALTCLKCTRL block?

Thanks, Olga

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Stratix IV - Error 176603: cannot place node at because it cannot...

December 7, 2014, 3:40 am

Hello all :]

I'm using Stratix IV [EP4SGX180KF40I3], with Quartus 11.1SP1.

I have two clock input pins: AB34 and AF6. I would like to choose between them using a CLKCTRL instance in the design [clock MUXing]. I used the ALTCLKCTRL block from the MegaWizard, with the following configuration: - For Global clock - 2 clock inputs - No enable port - No "Ensure glitch-free switchover" The SELECT port for the CTRLBLK was implemented with logic [could receive both '0' and '1' values].

When I run Quartus compilation, I receive the following error messages:

After getting the error message, I tried also to use a constant value for the SELECT ['0'], but I received again the same error.

Thanks, Olga

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Using PCIe on Cyclone V SX SoC Development Kit

December 7, 2014, 7:30 am

Hi,

I am new to PCIe, I would like to use PCIe provision on Cyclone V SX SOC dev. kit. Planning to plug a PCIe card and configure the dev kit to root port and communicate with other one.

please suggest any readily available pluggable PCIe altera based daughter card or any other solution to work with PCIe

Regards, phaniendra kundeti

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eclipse error

December 7, 2014, 12:49 pm

hello I made a project where i added NIOS processor and a memory i compiled the project succesfully but when am trying to run a simple BSP project i had this error on eclipse Failed to execute ./create-this-bsp--cpu-name nios2_qsys_0--no-make

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usb connection problem

December 8, 2014, 12:31 am

PC not detecting altera c3 fpga board when connected to usb port. before some time it was working fine..i also performed led blinking..but suddenly when i switch on today the kit., the leds start blinking very fast at a time and the load led is also illuminating..but hardware is not detected in pc..whats the problem and whats d soln..ii cheked using other cables and other pcs also..not working

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DPA Initial Phase in ALT_LVDS_RX core means what?

December 8, 2014, 1:01 am

Hi all.

I want to know that the setting about dpa_initial_phase [value:0 45 90 135 180 225 270 315 360] means the DPA circuit block will select a fixed shift phase[dpa_initial_phase] to sample rx data from alt_lvds_rx or DPA will select a better phase clock to sample rx data...? Does anyone know something about dpa_initial_phase setting ? Please share it to me . Thank you!:]

pofeng

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Error 12007 in Quartus with files from Megacore

December 8, 2014, 2:10 am

Dear Members I am working on harmonic detection with FFT.I am using FFT Megacore for that.This was generated using DSP builder Simulink. For simulation Matlab is used.Then i open Quartus.Files are added to the project. I am getting error: Error [12007]: Top-level design entity "lab1" is undefined. I have no idea what is top level entity in Mega core. I have gone through other posts.But still issue is unresolved.Thanks for help.

Best Regards

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Increasing the number of PCIe master address table entries

December 8, 2014, 6:11 am

The PCIe master [avalon slave] uses a lookup table to generate the high address bits for the PCIe master cycle. This does let us convert non-contiguous host memory [eg allocated with Linux vmalloc[]] into contiguous Avalon addresses. AFAICT this is just a internal memory block - so can have any [reasonable] size. However quartos 9.1 [I'm doing some experiments on an old project] only allows you to request table 512 entries, I'd really like 2048 entries [It only really makes sense to match the host page size of 4k].

Does anyone know if this restriction is still present in the quartos 13 [or 14]?

Or is there an easy way to edit the generated files [nasty I know] to increase the size. I think the size ends up as p_avalon_pane_count and uiPaneCount, editing the first might work. But I'd also need to change the Avalon slave addess map to increase the sizes of both slaves.

Anyone managed to hack this?

David

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MAX V & Board Test System

December 8, 2014, 6:15 am

Hello, I just got the MAX V kit. I'm learning to work with the kit. I installed quartus II 14.0 64 bit web edition on c:\Altera\14.0 folder . Also install the Max V develompent kit 11.1 on c:\altera\11.1\kits folder. I install the driver and can see it under device manager . USB Blaster. I plug the board to the PC USB and the blue light turn ON. Although , when I try to run Board Test System.exe software - nothing happens ?? No error , nothing hangs in the PC memory. simply nothing . Any reason ? I try on 2 computers Win7 64 bit .

Thanks , T.Z.

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Valid License for Dsp builder in Trial Version of Quartus

December 8, 2014, 8:32 am

Dear Members I was trying to simulate some tutorial examples. While compiling i get following error. Its something about license. I already have license for Matlab 2013. Do i need to have separate license for DSP builder. I am using Quartus trial version.Thanks for helping. ***************** Matlab Error Error using alt_dspbuilder_mdl2xml [line 36] Java exception occurred: com.altera.dspbuilder.common.DSPBuilderException: Unable to obtain a DSP Builder license. Please check that your LM_LICENSE_FILE environment variable is set to a valid license file or license server. LM_LICENSE_FILE is currently "". *******************

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procedure call problem

December 8, 2014, 8:43 am

Hi,

I am having problems using procedures in my simulation. I create the procedure between architecture and begin. I then call the procedure concurrently in the body of the architecture. As I understand it when I call the procedure like this then then it will be evaluated when any of the input signals change, a bit like a process with a sensitivity list. When I simulate however it seems to only evaluate once.

Here is a cut down of the code I am using:

Code:

`ARCHITECTURE logic OF test_procedure IS PROCEDURE read_stuff [ SIGNAL clk_i : IN std_logic; SIGNAL reset_i : IN std_Logic; SIGNAL empty : IN std_logic; SIGNAL rdreq : OUT std_logic] IS TYPE state_machine IS [ check_empty, clear_rdreq ]; VARIABLE state : state_machine; BEGIN IF[reset_i = '1'] THEN state := check_empty; rdreq