Error 12007 top level design entity test is undefined năm 2024
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Error (176603): Cannot place node CLK_125M_SEC at IOPAD_X119_Y43_N0 because it cannot drive the node HDP:U1|CLK_RESET_GEN:clk_rst|CLK125M_SEL:U3|CLK125 M_SEL_altclkctrl_lef:CLK125M_SEL_altclkctrl_lef_co mponent|sd2 placed at CLKSEL_G0 Show
Error (176603): Cannot place node CLK_125M at IOPAD_X0_Y52_N0 because it cannot drive the node HDP:U1|CLK_RESET_GEN:clk_rst|CLK125M_SEL:U3|CLK125 M_SEL_altclkctrl_lef:CLK125M_SEL_altclkctrl_lef_co mponent|sd2 placed at CLKSEL_G4 After getting the error message, I tried also to use a constant value for the SELECT ('0'), but I received again the same error. My questions are: - In general: Is it possible to drive these two input clock pins through a CLKCTRL block? - Do I have anything wrong in the ALTCLKCTRL block MegaWizard configuration? - Do I I have something wrong in the way I use the ALTCLKCTRL block? Thanks, Olga ↧ Stratix IV - Error 176603: cannot place node at because it cannot...December 7, 2014, 3:40 am Hello all :) I'm using Stratix IV (EP4SGX180KF40I3), with Quartus 11.1SP1. I have two clock input pins: AB34 and AF6. I would like to choose between them using a CLKCTRL instance in the design (clock MUXing). I used the ALTCLKCTRL block from the MegaWizard, with the following configuration: - For Global clock - 2 clock inputs - No enable port - No "Ensure glitch-free switchover" The SELECT port for the CTRLBLK was implemented with logic (could receive both '0' and '1' values). When I run Quartus compilation, I receive the following error messages: Error (176603): Cannot place node CLK_125M_SEC at IOPAD_X119_Y43_N0 because it cannot drive the node HDP:U1|CLK_RESET_GEN:clk_rst|CLK125M_SEL:U3|CLK125 M_SEL_altclkctrl_lef:CLK125M_SEL_altclkctrl_lef_co mponent|sd2 placed at CLKSEL_G0 Error (176603): Cannot place node CLK_125M at IOPAD_X0_Y52_N0 because it cannot drive the node HDP:U1|CLK_RESET_GEN:clk_rst|CLK125M_SEL:U3|CLK125 M_SEL_altclkctrl_lef:CLK125M_SEL_altclkctrl_lef_co mponent|sd2 placed at CLKSEL_G4 After getting the error message, I tried also to use a constant value for the SELECT ('0'), but I received again the same error. My questions are: - In general: Is it possible to drive these two input clock pins through a CLKCTRL block? - Do I have anything wrong in the ALTCLKCTRL block MegaWizard configuration? - Do I I have something wrong in the way I use the ALTCLKCTRL block? Thanks, Olga ↧ Using PCIe on Cyclone V SX SoC Development KitDecember 7, 2014, 7:30 am Hi, I am new to PCIe, I would like to use PCIe provision on Cyclone V SX SOC dev. kit. Planning to plug a PCIe card and configure the dev kit to root port and communicate with other one. please suggest any readily available pluggable PCIe altera based daughter card or any other solution to work with PCIe Regards, phaniendra kundeti ↧ ↧ eclipse errorDecember 7, 2014, 12:49 pm hello I made a project where i added NIOS processor and a memory i compiled the project succesfully but when am trying to run a simple BSP project i had this error on eclipse Failed to execute ./create-this-bsp--cpu-name nios2_qsys_0--no-make ↧ usb connection problemDecember 8, 2014, 12:31 am PC not detecting altera c3 fpga board when connected to usb port. before some time it was working fine..i also performed led blinking..but suddenly when i switch on today the kit., the leds start blinking very fast at a time and the load led is also illuminating..but hardware is not detected in pc..whats the problem and whats d soln..ii cheked using other cables and other pcs also..not working ↧ DPA Initial Phase in ALT_LVDS_RX core means what?December 8, 2014, 1:01 am Hi all. I want to know that the setting about dpa_initial_phase (value:0 45 90 135 180 225 270 315 360) means the DPA circuit block will select a fixed shift phase(dpa_initial_phase) to sample rx data from alt_lvds_rx or DPA will select a better phase clock to sample rx data...? Does anyone know something about dpa_initial_phase setting ? Please share it to me . Thank you!:) pofeng ↧ Error 12007 in Quartus with files from MegacoreDecember 8, 2014, 2:10 am Dear Members I am working on harmonic detection with FFT.I am using FFT Megacore for that.This was generated using DSP builder Simulink. For simulation Matlab is used.Then i open Quartus.Files are added to the project. I am getting error: Error (12007): Top-level design entity "lab1" is undefined. I have no idea what is top level entity in Mega core. I have gone through other posts.But still issue is unresolved.Thanks for help. Best Regards ↧ ↧ Increasing the number of PCIe master address table entriesDecember 8, 2014, 6:11 am The PCIe master (avalon slave) uses a lookup table to generate the high address bits for the PCIe master cycle. This does let us convert non-contiguous host memory (eg allocated with Linux vmalloc()) into contiguous Avalon addresses. AFAICT this is just a internal memory block - so can have any (reasonable) size. However quartos 9.1 (I'm doing some experiments on an old project) only allows you to request table 512 entries, I'd really like 2048 entries (It only really makes sense to match the host page size of 4k). Does anyone know if this restriction is still present in the quartos 13 (or 14)? Or is there an easy way to edit the generated files (nasty I know) to increase the size. I think the size ends up as p_avalon_pane_count and uiPaneCount, editing the first might work. But I'd also need to change the Avalon slave addess map to increase the sizes of both slaves. Anyone managed to hack this? David ↧ MAX V & Board Test SystemDecember 8, 2014, 6:15 am Hello, I just got the MAX V kit. I'm learning to work with the kit. I installed quartus II 14.0 64 bit web edition on c:\Altera\14.0 folder . Also install the Max V develompent kit 11.1 on c:\altera\11.1\kits folder. I install the driver and can see it under device manager . USB Blaster. I plug the board to the PC USB and the blue light turn ON. Although , when I try to run Board Test System.exe software - nothing happens ?? No error , nothing hangs in the PC memory. simply nothing . Any reason ? I try on 2 computers Win7 64 bit . Thanks , T.Z. ↧ Valid License for Dsp builder in Trial Version of QuartusDecember 8, 2014, 8:32 am Dear Members I was trying to simulate some tutorial examples. While compiling i get following error. Its something about license. I already have license for Matlab 2013. Do i need to have separate license for DSP builder. I am using Quartus trial version.Thanks for helping. ***************** Matlab Error Error using alt_dspbuilder_mdl2xml (line 36) Java exception occurred: com.altera.dspbuilder.common.DSPBuilderException: Unable to obtain a DSP Builder license. Please check that your LM_LICENSE_FILE environment variable is set to a valid license file or license server. LM_LICENSE_FILE is currently "". ******************* ↧ procedure call problemDecember 8, 2014, 8:43 am Hi, I am having problems using procedures in my simulation. I create the procedure between architecture and begin. I then call the procedure concurrently in the body of the architecture. As I understand it when I call the procedure like this then then it will be evaluated when any of the input signals change, a bit like a process with a sensitivity list. When I simulate however it seems to only evaluate once. Here is a cut down of the code I am using: Code: `ARCHITECTURE logic OF test_procedure IS PROCEDURE read_stuff ( SIGNAL clk_i : IN std_logic; SIGNAL reset_i : IN std_Logic; SIGNAL empty : IN std_logic; SIGNAL rdreq : OUT std_logic) IS TYPE state_machine IS ( check_empty, clear_rdreq ); VARIABLE state : state_machine; BEGIN IF(reset_i = '1') THEN state := check_empty; rdreq <= '0'; ELSIF(clk_i = '1' AND clk_i'EVENT) THEN CASE state IS WHEN check_empty => IF(empty = '0') THEN rdreq <= '1'; state := clear_rdreq; END IF; WHEN clear_rdreq => rdreq <= '0'; state := check_empty; END CASE; END IF; END PROCEDURE; SIGNAL clk : std_logic; SIGNAL reset : std_logic; SIGNAL empty_signal : std_logic; SIGNAL rdreq_signal : std_logic; BEGIN call_read_stuff : read_stuff ( clk_i => clk, reset_i => reset, empty => empty_signal, rdreq => rdreq_signal ); END ARCHITECTURE; ` The aim of the procedure is to read data from a fifo when it is not empty. I know I can do this with a process but I am trying to create a smaller reusable chunk that I can call in a generate as I have a few fifos that I want to pull data out of. This is for simulation only im not trying to create rtl from this. When I run my simulation the rdreq signal gets set when the empty flag goes low, however rdreq stays high, it doesnt seem to change to the second state and clear the rdreq signal and transition back to evaluate empty again. I also tried to do the same without using the state machine but had no more luck. Any suggestions would be appreciated. Thanks James ↧ ↧ How to get started with FPGA: Development tools?December 8, 2014, 2:17 pm Hi all, This is for Windows 7 Pro 64-bit. I want to get started with FPGA design so I thought I'll try the new MAX10 FPGA but every time I start reading FPGA stuff at Altera, I'm overwhelmed with the information available. A long time ago I bought a BeMicro because they said "5 easy steps to make a design...". Well... they wern't five (more like 50) and it sure as h*ll weren't easy. I felt I really didn't learn much so I gave up ... and sold it. I'm ready to try again and I have no expectation of anything being easy :-). I d/l Quartus II web edition v14 (Q14), plus the upgrade for MAX10. I know I need something for the NIOS II softcore, NDS? But the intallation of Q14 shows a NDS v14 installed. Is that the NDS I need...so I already have it? What about the software to write code for NIOS. Is Eclipse still in the picture or is Q14 all I need? Thanks ↧ Video Processing ProblemDecember 8, 2014, 8:55 pm I am using Cyclone III Development Board and I want to take an input from computer via Bitec DVI receiver and directly pass it to monitor via Bitec DVI transmitter. Here is the code, I used and I could not achieve what I want and have no idea why does it not work ? Appriciate your answers entity top is port( clk : in std_logic; BITEC_DVI_IO_IN : in std_logic_vector(23 downto 0); BITEC_DVI_IO_IN_DE : in std_logic; BITEC_DVI_IO_IN_HSYNC : in std_logic; BITEC_DVI_IO_IN_ODCK : in std_logic; BITEC_DVI_IO_IN_VSYNC : in std_logic; BITEC_DVI_IO_OUT_HSYNC : out std_logic; BITEC_DVI_IO_OUT_DE : out std_logic; BITEC_DVI_IO_OUT : out std_logic_Vector(23 downto 0); BITEC_DVI_IO_OUT_VSYNC : out std_logic; BITEC_DVI_IO_OUT_DVI_ISEL : out std_logic; BITEC_DVI_IO_OUT_DVI_PD : out std_logic; BITEC_DVI_IO_OUT_DVI_DKEN : out std_logic; BITEC_DVI_IO_OUT_DVI_CTL1 : out std_logic; BITEC_DVI_IO_OUT_DVI_CTL2 : 0ut std_logic; BITEC_DVI_IO_OUT_DVI_CTL3 : out std_logic; BITEC_DVI_IO_OUT_IDCKp : out std_logic; BITEC_DVI_IO_OUT_IDCKn : out std_logic ); end top; architecture behavioral of top is component vidout2 port ( is_clk : in std_logic := '0'; is_clk_rst.clk rst : in std_logic := '0'; is_clk_rst_reset.reset is_data : in std_logic_vector(23 downto 0) := (others => '0'); din.data is_valid : in std_logic := '0'; .valid is_ready : out std_logic; .ready is_sop : in std_logic := '0'; .startofpacket is_eop : in std_logic := '0'; .endofpacket vid_clk : in std_logic := '0'; clocked_video.export vid_data : out std_logic_vector(23 downto 0); .export underflow : out std_logic; .export vid_datavalid : out std_logic; .export vid_v_sync : out std_logic; .export vid_h_sync : out std_logic; .export vid_f : out std_logic; .export vid_h : out std_logic; .export vid_v : out std_logic .export ); end component; component vidin port ( is_clk : in std_logic := '0'; is_clk_rst.clk rst : in std_logic := '0'; is_clk_rst_reset.reset is_data : out std_logic_vector(23 downto 0); dout.data is_valid : out std_logic; .valid is_ready : in std_logic := '0'; .ready is_sop : out std_logic; .startofpacket is_eop : out std_logic; .endofpacket vid_clk : in std_logic := '0'; clocked_video.export vid_data : in std_logic_vector(23 downto 0) := (others => '0'); .export overflow : out std_logic; .export vid_datavalid : in std_logic := '0'; .export vid_locked : in std_logic := '0'; .export vid_v_sync : in std_logic := '0'; .export vid_h_sync : in std_logic := '0'; .export vid_f : in std_logic := '0' -- .export ); end component; signal locked :std_logic:='0'; signal c0,ready,valid,eop,sop,underflow,overflow,f,h,v: std_logic:='0'; signal data : std_logic_vector(23 downto 0):=(others=>'0'); begin l2: vidin port map(clk,'0',data,valid,ready,sop,eop,BITEc_DVI_IO_ IN_ODCK,BItEC_DVI_IO_IN,overflow,BITEC_DVI_IO_IN_D E,'1',BITEC_DVI_IO_IN_VSYNC,BITEC_DVI_IO_IN_HSYNC, f); l3: vidout2 port map(clk,'0',data,valid,ready,sop,eop,BITEc_DVI_IO_ IN_ODCK,BITEC_DVI_IO_OUT,underflow,BITEC_DVI_IO_OU T_DE,BITEC_DVI_IO_OUT_VSYNC,BITEC_DVI_IO_OUT_HSYNC ,f,h,v); BITEC_DVI_IO_OUT_IDCKp<=BITEC_DVI_IO_IN_ODCK; BITEC_DVI_IO_OUT_DVI_ISEL<='1'; BITEC_DVI_IO_OUT_DVI_PD <='0'; BITEC_DVI_IO_OUT_DVI_DKEN <='0'; BITEC_DVI_IO_OUT_DVI_CTL1 <='0'; BITEC_DVI_IO_OUT_DVI_CTL2 <='0'; BITEC_DVI_IO_OUT_DVI_CTL3 <='0'; BITEC_DVI_IO_OUT_IDCKn <='0'; end behavioral; ↧ Am I use the VERILOG FUNCTION correctly?December 8, 2014, 10:47 pm Hi:):), I'll be grateful and appreciate if somebody can help me to solve my problem. I'm a dummy in verilog and FPGA. Currently, I'm using Altera Cyclone IV to develop a IO card with PCI bus interface. I develop my code using state machine. The 32-bits data sent from the PC is being decoded based on the PCI byte enable signal before further processing in firmware. I'm using verilog function for decoding the data received from PC [function name: receiveDataFromPCI(benReg,l_dato)]. There will be another following post to show some part of my code of one of the state machine.
In first trial, I found out that dataReg register fail to give me the correct value even though benReg and l_dato signals are correct. Then, I changed to another way to write my code without using the verilog function:-
For the second trial, dataReg register changes its value based on benReg and l_dato signals as expected. Two version of the source file are attached in this thread. Here, are my doubts that really need to be advised: 1. I have mixed using blocking and non-blocking assignment in my first trial code. Blocking assignment is used in a function whereas non-blocking assignment is used in process block (always block). Am I using the verilog function correctly? 2. Although second trial code can function properly, any suggestion on how if I want to reuse the code? My code will become messy and not well-organised if I just simply copy and paste that portion of code in any where that I want to decode the data received via PCI bus. 3. Is it a good practice to using verilog function or task? I'm really look forward and appreciate somebody can provide his/her precious suggestion and advices. Thank you very much!:-P ↧ HELP: How to do not use sof file to download Nios softwareDecember 8, 2014, 10:56 pm My FPGA broad only have EPCS and SDRAM. And download Nios software need sof file. How to do not use sof file to download Nios software? Can I write a short bootloader to achieve this purpose? How? THANKS. ↧ ↧ 3G/GPRS module for Altera DE2-115 Dev BoardDecember 9, 2014, 1:01 am Hi, Can someone suggest cheap serial/USB based GPRS/3G module to transfer data from DE2-115 board to web or PC ? Are IP cores available for doing such things ? Thanks. BAS ↧ multipliers + RAM blocks limitationDecember 9, 2014, 1:34 am Is there a limitation on the number of embedded multipliers plus RAM blocks that can be used on a Cyclone IV? In some FPGAs (such as SPARTAN 3E) a data bus is shared between multipliers and RAM blocks, so you can use either one or the other. That implies that the number of multipliers plus the number of RAM blocks that can be used is limited. Is this limitation present in other FPGAs? ↧ How to divide tasks to be done by Nios II processor & Logic elements?December 9, 2014, 2:13 am Hi all, I have a complete working project where I use MATLAB/Simulink with coding in S-function Level 2 as well as Simulink blocks. Now I would like to convert the above project into C AND VHDL to be implemented on a hardware FPGA design on DE0 Nano Development board, Cyclone IV E. I am using Quartus II, SOPC builder, Nios II IDE or Altera monitor program. In my Matlab project, basically what I was doing is to have thousand of inputs, sort them ascending/descending, do some comparison if-else, arithmetic operations, produce outputs, switching on/off devices. (I could give more details about this, the number of inputs/outputs could be reduced to the size permissible by hardware) What I know: I am going to use BOTH the Nios II processor AND the logic elements on the development board, meaning I need to program Nios II using C language AND also program those logic elements using VHDL. What I don't know: My question is, how do I determine which tasks are to be done by Nios II processor and which tasks are to be done by logic elements? Is there specific rule to follow or is it totally up to the programmer to decide? But I guess there should at least be some basic rules to adhere? How do you define topA design entity that is the root of a design hierarchy. To compile or simulate a design, you compile or simulate the top-level design entity. A top-level design entity can contain any number of lower-level design entities (or, subdesigns), and is the parent for the lower-level design entities. How do I change the topIn Quartus II, use "Project --> Set as Top-Level Entity" to change the top-level entity to different VHDL example. Alternatively, highlight the VHDL file name in the "Project Navigator" and right click to select "Set as Top-Level Entity". |
